ini program saya!! updowncounter 16bit Verilog HDL

module pengira(enable,clk,clk_out,reset,count,seven_seg1, seven_seg2, seven_seg3,seven_seg4,seven_seg5);
input enable, clk,reset; // declaration for input
output reg [15:0] count;   //declare out as register
reg [3:0] bcd1,bcd2,bcd3,bcd4,bcd5;  //declare bcd1,bcd2,bcd3,bcd4,bcd5 as register
           
output clk_out;  //declare clk_out as a wire
           
output [6:0] seven_seg1,seven_seg2,seven_seg3,seven_seg4,seven_seg5;//declaration for output



frequencydev (clk,clk_out); //subprogram for frequency division

always @ (posedge clk_out)//clk

    if (reset) begin           //main program for counter
    count <= 0;
    end

    else if (enable) begin     // program for count up
    count <= count+ 1;
    end

    else begin    //program for count down
    count <=count-1;
    end

always@(*)   //ready to change when call

    begin                                      // program for bcd change to decimal
    bcd5=((count-(count%10000))/10000)%10;         //MSB (Most significant bit)
    bcd4=((count-(count%1000))/1000)%10;
    bcd3=((count-(count%100))/100)%10;
    bcd2=((count-(count%10))/10)%10;
    bcd1=count%10;                              //LSB (Least significant bit)
    end

    sevensegment s1(bcd1,seven_seg1);   //call first bit seven segment
    sevensegment s2(bcd2,seven_seg2);   //call second bit seven segment
    sevensegment s3(bcd3,seven_seg3);   //call third bit seven segment
    sevensegment s4(bcd4,seven_seg4);   //call fourth bit seven segment
    sevensegment s5(bcd5,seven_seg5);   //call fifth bit seven segment

endmodule